Electric VLSI Design System

The system provides a comprehensive set of tools for creating and verifying integrated‑circuit designs. It supports custom layout creation, schematic capture, and hardware‑description‑language editing, while also offering design‑rule and electrical‑rule checking. Simulation capabilities are built in and can be extended with external simulators, with waveform displays for analysis. Generation functions produce ROMs, PLAs, pad frames, fill patterns, implant coverage, and other layout elements, and the suite includes placement, routing, and network‑consistency (LVS) checking, as well as logical‑effort analysis and compaction utilities.

It is suitable for engineers and researchers working on a wide range of IC technologies, from traditional nMOS, bipolar, and BiCMOS processes to modern CMOS variants, thin‑film, carbon‑nanotube, and photonic structures. The tool also accommodates abstract designs such as digital filters and temporal logic, making it useful for both low‑level physical layout and higher‑level functional modeling.

The software handles numerous industry file formats for import and export, including CIF, GDS, EDIF, LEF/DEF, DXF, Gerber, VHDL, Verilog, and can produce outputs compatible with EAGLE, PADS, ECAD, as well as graphics formats like PostScript, SVG, HPGL, and PNG. Implemented in Java, it runs on all operating systems, and the current stable release is targeted at